Cypress Semiconductor /psoc63 /FLASHC /FM_CTL /ACLK_CTL

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Interpret as ACLK_CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ACLK_GEN)ACLK_GEN

Description

Aclk control

Fields

ACLK_GEN

A write to this register generates a ACLK pulse for the flash macro (also requires FM_CTL.IF_SEL to be ‘1’).

Links

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